VHDL:进程块内的多个rising_edge检测

我是VHDL(以及一般的数字电路)的新手,我正在尝试使用BCD样式块实现两位数的计数器.在这个电路的外部会有按钮,当按下时,按钮会使感兴趣的数字上升一个(很像闹钟).这是一个异步操作,在某种形式的编辑模式(外部强制执行)时会发生.我写的代码没有“elsif rising_edge(digitUp1)then”和“elsif rising_edge(digitUp1)然后”阻止工作正常,但包含它们失败了.我真的不知道为什么它不起作用或我如何解决它.继续得到诸如“无法在此时钟边沿上实现分配寄存器”之类的错误,“无法推断count2 [3]的寄存器,因为它的行为取决于多个不同时钟的边沿”和“无法推断寄存器为” count2 [3]“在MinuteCounter.vhd(21)因为它没有在时钟边缘之外保持其值”.任何帮助将不胜感激.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

-- ToDo: ENFORCE ON ALL COUNTERS (externally) LOGIC TO PAUSE AT MAX/MIN

entity MinuteCounter is
port( clockIn, digitUp1, digitUp2, reset, counting, countUp : in std_logic;
      clockOut : out std_logic;
      BCD1, BCD2 : out std_logic_vector(3 downto 0));
end MinuteCounter;

architecture structure of MinuteCounter is
signal count1, count2 : std_logic_vector(3 downto 0);
signal carryOut : std_logic;
begin

process( clockIn, digitUp1, digitUp2, countUp, reset, counting)
begin 

    -- Asynchronous reset
    if reset = '1' then
        count1 <= "0000";
        count2 <= "0000";

    -- What to run when there's an active edge of the clock
    elsif rising_edge(clockIn) then

        -- Code to run when timer is running
        if counting = '1' then

            -- What to do when counting up
            if countUp = '1' then
                if ((count1 = "1001") and (count2 = "0101")) then
                    count1 <= "0000";
                    count2 <= "0000";
                    if carryOut = '0' then
                        carryOut <= '1';
                    else
                        carryOut <= '0';
                    end if;
                elsif count1 = "1001" then
                    count1 <= "0000";
                    count2 <= count2 + 1;
                else
                    count1 <= count1 + 1;
                end if;

            -- What to do when counting down (This logic is hard to understand)
            else
                if ((count1 = "0000") and (count2 = "0000")) then
                    count1 <= "1001";
                    count2 <= "0101";
                    if carryOut = '0' then
                        carryOut <= '1';
                    else
                        carryOut <= '0';
                    end if;
                elsif count1 = "0000" then
                    count1 <= "1001";
                    count2 <= count2 - 1;
                else
                    count1 <= count1 - 1;
                end if;
            end if;

        -- When counting is disabled, but there is an active edge (do nothing)
        else
            count1 <= count1;
            count2 <= count2;
        end if;

    -- Code to run when entering values (will not be run if counting = '1') << Externally enforced
    elsif rising_edge(digitUp1) then
        if count1 = "1001" then
            count1 <= "0000";
            count1 <= count1 + 1;
        else
            count1 <= count1 + 1;
        end if;

    -- Code to run when entering values (will not be run if counting = '1') << Externally enforced
    elsif rising_edge(digitUp2) then
        if count2 = "0101" then
            count2 <= "0000";
            count2 <= count2 + 1;
        else
            count2 <= count2 + 1;
        end if;

    -- What to do when there is no active edge or other events (nothing)
    else
        count1 <= count1;
        count2 <= count2;
    end if;

end process;

-- Assign outputs
BCD1 <= count1;
BCD2 <= count2;
clockOut <= carryOut;

end structure;
最佳答案
问题标题中解释了“为什么它不起作用”:进程块内的多个rising_edge检测.

VHDL旨在描述硬件,并且没有响应多个时钟信号的基本电路元件.所以你无法用这种方式描述电路.

那么你如何解决它?

您可以将电路转换为任何单个进程只有一个时钟信号(并且可选地,正确使用一个异步复位信号)的电路.这可以使用实际寄存器和触发器来实现.

两种方式是:

>几个过程,使用信号在它们之间进行通信
>单个进程,使用单个时钟,对主时钟边沿的其他信号进行采样.

这些之间的正确决定需要对设计有一些全面的了解.

这听起来好像所有三个时钟信号实际上是按下按钮,而不是一个快速时钟.因此,您无法保证在按下另一个按钮时会有时钟边沿.

所以这是前进的众多方法之一:制作一个时钟信号(在过程之外),它将覆盖所有三个输入事件.

my_clock <= clockIn or digitUp1 or digitUp2;

现在您可以使用此时钟重写该过程:

process(my_clock, reset) is
begin
   if reset = '1' then
      -- reset actions
   elsif rising_edge(my_clock) then
      -- what caused this event?
      if digitUp1 = '1' then      -- bump digit 1
      elsif digitup2 = '1' then   -- bump digit 2
      else                        -- count normally
      endif;
   end if;
end process;

笔记:

>由于这是一个正确的同步过程,因此只有时钟和重置属于灵敏度列表.
>虽然这在某种意义上是有效的,但它可能不是客户想要的:如果他按下所有三个按钮会发生什么?您可能想要探索其他设计方法.

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